A conventional approach to building a multichip computer system comprises the steps of designing and fabricating a set of integrated circuits based on the system's architecture, finding or building carrier packages for the IC chips, and creating a custom routed circuit board (e.g., printed wiring board) to interconnect the IC chips, or alternatively creating a custom routed multichip module that houses the IC chips. In general, the tasks of providing carrier packages and interconnections between the IC chips is given secondary priority to the designing of the IC chips. Further, these tasks are generally given little, if any, consideration in the design of the IC chips. As one example, the assignment of signal lines to the chip's available I/O pads is primarily determined by the chip's circuitry and the desire to reduce the surface area needed to implement the circuitry. Secondary consideration, if any, is given to how the assignment of signal lines to the I/O pads might affect the cost, yield, and manufacturability of the IC chip packaging and interconnection.
Great emphasis has been placed on laying-out the circuitry to minimize area so as to reduce manufacturing costs and increase chip yields by obtaining more IC chips per wafer. It is generally believed in the art that the packaging costs are lower than the costs of manufacturing the IC chips. However, the packaging often has to be re-worked to replace malfunctioning IC chips or to repair bad connection points. The IC chips are usually tested with only DC or slow-speed signals generated by a testing unit, and are not tested with the types of high-speed signals present in the system. Therefore, even though an IC chip may pass the "DC" test, it may malfunction in the system. Additionally, the IC chips are usually attached to test substrates for the testing. After testing, the chips are de-attached and subsequently attached to carrier substrates or MCM modules. The detachment and subsequent attachment processes can damage the interconnect pads or the chip, resulting in a malfunctioning chip. Significant time can be spent locating malfunctioning chips and defective connections in the assembled system. This time, and the time spent re-working, add significant hidden costs to the packaging tasks, and are often overlooked when comparing chip manufacturing costs to packaging costs.
There has been some suggestions in the art that a universal interconnect substrate could be created which could be customized by fusing and/or bonding wires on the surface of the universal interconnect substrate to provide a customized set of interconnections to the IC chips. Unfortunately, these suggestions usually are not manufacturable or do not have enough wiring density to be successful.
The above packaging issues apply not only to multi-chip computer systems, but to special electronic processors and other electronic systems requiring the interconnection of several IC chips (including analog systems and hybrid digital/analog systems).